The usage of digital signal processing techniques for recovery of digital information from an analogue recording or transmission signal is as such known from the prior art. For example, U.S. patent application 20020122478A1, which is incorporated herein in its entirety, shows a signal-processing circuit and a recording and playback apparatus employing the same. A two-stage equalisation is carried out by using first and second equalisation circuits provided on the upstream and downstream sides from a phase-locked loop circuit.
The first equalisation circuit on the upstream side from the phase-locked loop circuit is composed of a transversal filter, to minimise an equalisation error caused by the first equalisation circuit in order to stabilise the operation of the phase-locked loop circuit. Another signal-processing circuit including an analogue-to-digital converter and a digital phase-locked loop circuit for receiving the output from the analogue-to-digital converter and a recording and playback apparatus using the same are also disclosed, wherein the output from the analogue-to-digital converter is input as the digital signal in the digital phase-locked loop circuit in order to fetch a detection point voltage for stabilisation of the operation of the phase-locked loop circuit.
The digital FIR upstream of the timing recovery block can be adapted gradually and periodically in the over-sampled domain but not in real time. Usage of a synchronous adaptive FIR filter after the timing recovery block in order to adapt the synchronous errors, and then convolving the adapted FIR response with that of the FIR upstream of the timing recovery block to derive a new response for the FIR upstream of the timing recovery block is costly, as two FIR filters are required, and complicated as convolution algorithms are relatively expensive to be part of a feedback loop. Another substantial disadvantage is the required expense in terms of silicon space and the relatively high power consumption and power dissipation.